Motorola VL-RISC MCF5202 - Manual (Page 3)

MOTOROLA GATEWAY BOARD 3
cache mode to cache-inhibit. This will require the microprocessor to go to external memory to get accurate data as
opposed to having a cache hit within internal memory which could possibly contain stale data.
2.1.3 RMW cycles
If the TAS instruction is used in the original M68000 code for implementing the locked or read-modify-write
transfer sequence in hardware, then new code will have to be written that essentially implements the same locked
transfer in software. This can be done by raising the interrupt mask to 7 and then executing the read, modify, and
write instructions, and then lowering the mask back down to the appropriate level. This will ensure that the sequence
of instructions between the raising and lowering of the mask will execute uninterrupted, except for a level 7 interrupt
which is nonmaskable.
2.2 Hardware Considerations
The target system must have a female 68-pin PLCC socket such that it could hold a 68EC000 PLCC FN pack-
age not a 68EC000 QFP FU package. The Gateway board has a male connector arranged in a PLCC FN fashion that
will sit in this socket. The Gateway board can operate in 8- or 16-bit data mode. The board can handle interrupt
acknowledge cycles for external vector number acquisition or the AVEC* signal can be used to allow internal vector
generation. One difference between the MCF5202 and the 68EC000 is that DA*[1:0] is always asserted whether
AVEC* is asserted or not. Also, the interrupt level being acknowledged is driven onto A/D[4:2] by the MCF5202,
which has to be routed onto address lines A[3:1] for the 68EC000. See Figure 3 for more details. The board also has
control logic to handle bus arbitration for alternate bus masters. If the HALT signal is asserted, the processor will
stop bus activity at the completion of the current bus cycle and will place all control signals in the inactive state and
place all three-state lines in the high-impedance state.
3.0 Performance
The Gateway board performance will be Þrst discussed generally and then speciÞcally with an industry-stan-
dard benchmark. For each bus cycle, there is one extra clock required from the beginning of the ColdFire MCF5202
microprocessor bus cycle to the beginning of the 68EC000 bus cycle. This is due to the multiplexed ATM signal on
the ColdFire which is required to create the FC signals on the 68EC000 bus. Also, there are some bus clocks inherent
to the ColdFire cycle that occur after the 68EC000 bus cycle is done. This is zero to two extra clocks, depending on
the size of the access and whether the access is a read or a write. Therefore, because the fastest possible bus transac-
tion for the 68EC000 is 4 bus clocks, the fastest Gateway board bus transaction can be as few as 5 bus clocks for the
Þrst bus access of a longword write, or as many as 7 bus clocks if doing, for example, a single byte read. Table 2 and
Table 3,compare all possible combinations of accesses between the MCF5202 and the MC68EC000.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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