Motorola VL-RISC MCF5202 - Manual (Page 12)

12 GATEWAY BOARD MOTOROLA
ATMA.clk = TS; "ATM is latched when TS is asserted
NQ1.ar = RSTI;
NQ2.ar = RSTI;
NQ1.clk= PCLK; "Clock NegClk machine 1 with pos clk
NQ2.clk= !PCLK; "Clock NegClk machine 2 with the inverted pos clk
bsreg.clk = PCLK;
bsreg.ar = RSTI;
"Output enables
AS.oe = !BG68K; Òenable when the 68K is not granted the bus
UDS.oe = !BG68K; Òenable when the 68K is not granted the bus
LDS.oe = !BG68K; "enable when the 68K is not granted the bus
FC0.oe = !BG68K; "enable when the 68K is not granted the bus
FC1.oe = !BG68K; "enable when the 68K is not granted the bus
FC2.oe = !BG68K; "enable when the 68K is not granted the bus
"Sequential Logic
A0 := AD0;
ATMA := ATM;
NQ1 := !NQ1;
NQ2 := NQ1;
"-----------------------------------------------------------------------------------------
"Combinational Logic - (See NOTE 2)
NCLK = NQ1 !$ NQ2; "XNOR the outputs of the two NegClk state machines to produce NCLK
" AS is asserted for PS3, PS4, and the posclk of PS5
AS = PSTATE3 # PSTATE4 # PSTATE5&!NCLK;
" OEBA16 = (CF is master & not halted & during AS)&(16-bit read & !IACK)
OEBA16 = (!BG68K & !HALT & AS) & ( RnW&MODE & !(TT1 & TT0) );
" OEBA8 = (CF is master & not halted & during AS)&(8-bit read # IACK)
OEBA8 = (!BG68K & !HALT & AS) & ( RnW&!MODE # TT1&TT0 );
" OEAB16 = (CF is master & not halted & during AS)&(16-bit write)
OEAB16 = (!BG68K & !HALT & AS) & ( !RnW&MODE );
" OEAB8 = (CF is master & not halted & during AS)&(8-bit write
OEAB8 = (!BG68K & !HALT & AS) & ( !RnW&!MODE );
" UDS = (Read&PS3 # PS4 # PCLK&PS5) & (16-bit) & !( Odd & Byte )
UDS = (RnW&PSTATE3 # PSTATE4 # PSTATE5&!NCLK) & MODE & !( A0 & !SIZ1&SIZ0 );
" LDS = (Read&PS3 # PS4 # PCLK&PS5) & !(16-bit & Even & Byte & !IACK)
LDS = (RnW&PSTATE3 # PSTATE4 # PSTATE5&!NCLK) & !( MODE & !A0 & !SIZ1&SIZ0 & !(TT1&TT0) );
DA1 = PSTATE5 & MODE; "PS5 & 16-bit
DA0 = PSTATE5 & !MODE; "PS5 & !16-bit
LDAT = PSTATE5 & NCLK; "PS5 & NCLK
"ADLT = (TS&PS1 # PS2 # PS3 # PS4 # PCLK&PS5)
ADLT = (TS&PSTATE1 # PSTATE2 # PSTATE3 # PSTATE4 # PSTATE5&!NCLK);
AENORM = (!BG68K & !HALT) & !(TT1&TT0); "(CF is master & not halted) & !(IACK-Access)
AEIACK = (!BG68K & !HALT) & (TT1&TT0); "(CF is master & not halted) & (IACK-Access)
AEUP = (!BG68K & !HALT); "(CF is master & not halted)
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Freescale Semiconductor, Inc.
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