Mitel DISTRIBUTED HYPERCHANNEL MT90840 - Manual (Page 13)

Preliminary Information
MT90840
2-243
The transmit path does not provide an elastic buffer,
and therefore the serial port clock must be tightly
locked (in frequency) to the parallel port clock
(PCKR). (Jitter less than +/- 100nsec.) This may be
achieved in one of two ways: use of the internal clock
divider (INTCLK set high), or use of an external PLL
or DPLL, with C4 phase-correction performed by the
MT90840.
Internal 4.096 MHz Clock Divider
For TM2 applications at 19.44 or 16.384 MHz rates
on the parallel port, and 4.096 MHz on the serial
port, the internal clock divider can be enabled. The
clock divider can generate the required serial port
clock outputs from the parallel port clock inputs.
When enabled in TM2, the clock divider will provide
4.096 MHz (SPCKo) and 8 kHz (F0o) timing to the
serial port that is rigidly locked to the PCKR and
PPFRi clocks at the parallel port. The clock divider is
enabled by setting the INTCLK bit high (in the TIM
Register). The clock divider can not be used in
applications where the parallel port operates at
6.480 Mbyte/s rates.
External PLL and C4 Phase-Correction
The MT90840 also supports the use of an external
PLL (e.g. MT9041/2) to generate 4.096 or 8.192 MHz
from the parallel port timing reference. At 4.096 MHz
the generated clock must be input to the MT90840
(at C4/8R1 or C4/8R2) for phase monitoring and
correction. The phase-corrected 4.096 MHz clock is
then output on the SPCKo pin. Should the phase of
the C4clock input (relative to the PPFRi framing
input) drift more than approximately +/- 100nsec, the
MT90840 will apply an additional correction and
indicate possible data corruption with the RXPAA
interrupt source. At 8.192 MHz, the generated clock
is input to the MT90840 (at C4/8R1 or C4/8R2), and
is also supplied directly to the serial bus (the SPCKo
output is not used at 8.192 MHz). The serial port
frame pulse (F0o) will be slaved to the parallel port
frame pulse (PPFRi), and will be clocked out by
SPCKo, or the 8.192 MHz clock, as appropriate.
TM2 Multiple-MT90840 Sub-Mode (SFDI)
For TM2 applications which require more serial
channels than are provided by a single MT90840, it
is possible to operate multiple MT90840s in parallel.
Multiple-MT90840 operation is automatic if INTCLK
is selected, but if an external PLL is used, the serial
port timing of the MT90840s must be synchronized.
To do this, one MT90840 controls the PPFRi-to-F0o
timing and C4 phase-control (normal TM2), and the
remaining MT90840s must synchronize to the first by
using F0 as an input reference. The device providing
the reference will have the SFDI bit in the TIM
Register set low (normal TM2). All other MT90840s
will have SFDI set high (forcing F0 to be an input).
Figure 6b shows this mode using two MT90840s;
additional MT90840s (with SFDI set high) may be
added. This sub-mode allows the serial ports of the
multiple TM2 MT90840s to share one timing source.
The transmit parallel port outputs are always
synchronized to PPFRi in TM2, so the multiple
MT90840s can also be connected together on one
parallel output bus.
The TM2 Multiple-MT90840 sub-mode is not
available for operation at 6.48 Mbyte/s.
Figure 6a - Timing Mode 2 Configuration
8
8
8 kHz TX
Data TX
8 kHz RX
Data RX
PCKR
PPFT
PDo0-7
PDi0-7
PPFRi
STi0-7
STo0-7
SPCKo
F0o
8 STi/o 0-7
8 STi/o 0-7
8 kHz
4.096 MHz
MT90840
CPU
TX/RX Clock
C4/8R1 & 2
PLL
4.096 MHz or
8.192 MHz
Note: the use of an external PLL is optional at 4.096 MHz (2.048 Mbps and 4.096 Mbps)
ST-BUS
Components
8 kHz
Source
(8.192 MHz)