Mitel DISTRIBUTED HYPERCHANNEL MT90840 - Manual

2-231

Features
• Time slot interchange function between eight
pairs of ST-BUS/GCI/MVIP

streams (512
channels) and parallel data port
• Programmable data rates on the parallel port
(19.44, 16.384, or 6.480 Mbyte/s)
• Programmable data rates on the serial port
(2.048 Mbps, 4.096 Mbps or 8.192 Mbps)
• Supports star and point-to-point connections, and
unidirectional or bidirectional ring topologies for
distributed systems
• Input-to-output bypass function on the parallel
data port for use in add/drop applications
• Provides elastic buffer at parallel input port in the
receive direction
• Provides byte switching for up to 2430 channels
• Per-channel direction control on the serial port
side
• Per-channel message mode and high-impedance
control on both parallel and serial port sides
• 8-bit multiplexed microprocessor port compatible
with Intel and Motorola microcontrollers
• Guarantees frame integrity when switching nX64
wideband channels such as ISDN H0 channel
• Provides external control lines allowing fast
parallel interface to be shared with other devices
• Diagnostic alarm functions and clock
phase-status word for clock monitoring
• IEEE 1149 (JTAG) boundary scan port
Applications
• Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplexed backplanes at
SONET rates (STS-1, STS-3)
• High speed isochronous backbones for
distributed PBX and LAN systems
• Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
• Serial bus control and monitoring
• Data multiplexing
• High speed communications interface
ISSUE 2 March 1997
Ordering Information
MT90840AL 100 Pin PQFP
MT90840AP 84 Pin PLCC
-40
°
C to 85
°
C
Figure 1 - Functional Block Diagram
MT90840
Distributed Hyperchannel Switch
Output
Mux &
PDo0
PDo7
2430 Position
TX Path
Connection Memory
Bidirectional
I/O
Driver
8 Serial
to
Parallel
&
Parallel
to
Serial
Conver-
Bidirectional
I/O
Driver
STi7
STi0
STo7
STo0
4
CTo0-3
Timing
Control
Unit
PDi0
PDi7
PCKR
PCKT
RES
PPFRi
PPFTi/o
F0i/o CPU Interface
Internal
Registers
TEST
Pins
5
8 8
SPCKo C4/8R1 C4/8R2
IRQ
AD0-7
R/W\WR AS/ALE
CS
DTA VDD VSS
DS/RD
ters
Multiple Pages of 512 Position
TX Path Data Memory
8
512 Position
RX Path
8
Multiple Pages of 2430-Byte
RX Path Data Memory
15
8
8
Connection Memory
JTAG
Drivers
16
Preliminary Information