HP BL460C G7 - Manual (Page 31)

Hardware options installation 31
Mirrored memory configuration
Mirroring provides protection against uncorrected memory errors that would otherwise result in server blade
downtime. Mirroring is performed at the channel level. Channels 1 and 2 are used; channel 3 is not
populated.
Data is written to both memory channels. Data is read from one of the two memory channels. If an
uncorrectable error is detected in the active memory channel, data is retrieved from the mirror channel. This
channel becomes the new active channel, and the system disables the channel with the failed DIMM.
Lockstep memory configuration
Lockstep mode provides protection against multi-bit memory errors that occur on the same DRAM device.
Lockstep mode can correct any single DRAM device failure on x4 and x8 DIMM types. The DIMMs in each
channel must have identical HP part numbers.
Lockstep mode uses channel 1 and channel 2. Channel 3 is not populated. Because channel 3 cannot be
populated when using Lockstep mode, the maximum memory capacity is lower than Advanced ECC mode.
Memory performance with Advanced ECC is also slightly higher.
Online Spare memory configuration
Online spare memory provides protection against degraded DIMMs by reducing the likelihood of
uncorrected memory errors. This protection is available without any operating system support.
Online spare memory protection dedicates one rank of each memory channel for use as spare memory. The
remaining ranks are available for OS and application use. If correctable memory errors occur at a rate
higher than a specific threshold on any of the non-spare ranks, the server blade automatically copies the
memory contents of the degraded rank to the online spare rank. The server blade then deactivates the failing
rank and automatically switches over to the online spare rank.
General DIMM slot population guidelines
Observe the following guidelines for all AMP modes:
• Populate DIMM slots for a processor only if the processor is installed.
• To maximize performance in multi-processor configurations, distribute the total memory capacity
between all processors as evenly as possible.
• Do not mix Unbuffered and Registered PC3 DIMMs.
• Each channel supports up to two Unbuffered DIMMs.
• If quad-rank DIMMs are installed for a processor, a maximum of two DIMMs can be installed on each
channel for that processor.
If a channel contains quad-rank DIMMs, the quad-rank DIMM must be installed first on that channel.
DIMM speeds are supported as indicated in the following table.
Populated slots
(per channel)
Rank Speeds supported
(MHz)
1 Single- or dual-rank 1333, 1066
1 Quad-rank 1066
2 Single- or dual-rank 1066