HP SL6000 - Manual (Page 11)

Multi-level caches
Intel Xeon 5500 Series processors have a three-level cache hierarchy (Figure 9):
•
An on-core 64-kilobyte Level 1 cache, split into two 32-kilobyte caches: one for data and one for
instructions
• 256-kilobyte, Level 2 cache for each core to reduce latency
• A Level 3 cache of up to 8 megabytes
Figure 9. Block diagram of
three-level cache hierarchy for Intel Xeon 5500 Series processors
The Level 3 cache is shared by all cores. It is inclusive, which means that it duplicates the data stored
in each core’s Level 1 and 2 caches. This duplication minimizes latency by eliminating unnecessary
core snoops to the Level 1 and 2 caches. Flags in the Level 3 cache track the cache source of data. If
one core modifies another core’s data in Level 3 cache, the Level 1 and 2 caches of those cores are
updated as well. This eliminates excessive inter-core traffic and ensures multi-level cache coherence.
Integrated memory controller
Instead of sharing a single pool of system memory, each processor accesses its own dedicated DDR3
system memory directly through an integrated memory controller. Three memory channels from each
memory controller to its dedicated DDR3 memory provide a total bandwidth of 32 gigabytes per
second. The three memory channels eliminate the bottleneck associated with earlier processor
architectures in which all system memory access was through a single memory controller over the front
side bus. When needed, a processor can access another processor’s memory through the QuickPath
Interconnect.
11