Avago Technologies LSI53C810AE User Manual

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Bit 15 PME Status (PST)

The device always returns a 0 for this bit, indicating that PME signal generation is not sup-
ported from D3cold.

Bits 14-13 Data Scale (DSCL)

The device does not support the Data register, therefore this field is always set to 00b.

Bits 12-9 Data Select (DSLT)

The device does not support the Data register, therefore this field is always set to 0000b

Bit 8 PME Enable (PEN)

The device always returns a 0 for this bit to indicate that PME assertion is disabled.

Bits 7-2 Reserved

Bits 1-0 Power State (PWS)

This two bit field determines the current power state for the function and is used to set the
function to a new power state. The definitions of the field values are:
00b - D0
01b - Reserved
10b - Reserved
11b - D3hot

BSE

Default >>>

This register can support PCI bridge specific functionality if required. The default value always
returns 00h.

This register provides an optional mechanism for the function to report state-dependent operating
data. The default value is 00h.

This is currently not implemented for these devices.