Avago Technologies LSI53C810AE - Manual (Page 5)

5
Register 08h
Revision ID
Read Only
RID RID RID RID RID RID RID RID
7 6 5 4 3 2 1 0
Default >>>
0 0 1 0 0 0 1 1
This field specifies device and revision identifiers. The value of this register is
23h.
Register 34h
Capability Pointer
Read Only
CP CP CP CP CP CP CP CP
7 6 5 4 3 2 1 0
Default >>>
0 1 0 0 0 0 0 0
This register provides an offset into the function’s PCI Configuration Space for the location of
the first item in the capabilities linked list. This register is set by the device to 40h.
Register 40h
Capability ID
Read Only
CID CID CID CID CID CID CID CID
7 6 5 4 3 2 1 0
Default >>>
0 0 0 0 0 0 0 1
This register indicates the type of the current data structure (linked list item). This register is set
by the device to a value of 01h, indicating the Power Management Data Structure.
Register 41h
Next Item Pointer
Read Only
NP NP NP NP NP NP NP NP
7 6 5 4 3 2 1 0
Default >>>
0 0 0 0 0 0 0 0
This register describes the location of the next item in the function’s capability list. This register
is set by the device to a value of 00h, indicating that power management is the last capability in
the linked list of extended capabilities.