Avago Technologies LSI53C810AE - Manual (Page 6)

6
Register 42h
Power Management Capabilities
Read Only
PMES D2S D1S RES DSI APS PMEC VER
15-11 10 9 8-6 5 4 3 2-0
Default >>>
0 0 0 0 0 0 0 1
This register indicates the power management capabilities.
Bits 15-11 PME Support (PMES)
This field always returns a zero value because the devices do not provide a PME signal.
Bit 10 D2 Support (D2S)
This device does not support the D2 power management state.
Bit 9 D1 Support (D1S)
This device does not support the D1 power management state.
Bits 8-6 Reserved
Bit 5 Device Specific Initialization (DSI)
This bit is set to 0 to indicate that the device requires no special initialization before the generic
class device driver is able to use it.
Bit 4 Auxiliary Power Source (APS)
Because the device does not provide a PME signal, this bit always returns a 0. This indicates that
no auxiliary power source is required to support the PME signal in the D3cold power
management state.
Bit 3 PME Clock (PMEC)
This bit always returns a 0b value because the SYM53C810AE does not provide a PME signal.
Bits 2-0 Version (VER)
This field is set to 001b to indicate that the device complies with Revision 1.0 of the PCI Power
Management Interface Specification.
Register 44h
Power Management Control/Status
Read/Write
PST DSCL DSLT PEN RES PWS
15 14-13 12-9 8 7-2 1-0
Default >>>
0 0 0 0 0 0
This register indicates the power management control and status descriptions.