1 overview, 2 hba features, 3 functional descriptions – Avago Technologies SAS 9200-8e Host Bus Adapter User Manual
Page 4: 1 pcie, 1overview, 2hba features, 3functional descriptions
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LSI SAS 9200-8e PCI Express to 6Gb/s SAS HBA User Guide
October 2014
Overview
LSI SAS 9200-8e PCI Express to 6Gb/s SAS HBA User Guide
1
Overview
The LSI SAS 9200-8e PCI Express® (PCIe®) to Serial Attached SCSI (SAS) host bus adapter (HBA), hereinafter referred to
as the LSI SAS 9200-8e HBA, provides high-performance external storage connectivity for servers and workstations.
The LSI SAS 9200-8e HBA provides eight lanes of 6Gb/s SATA or SAS connectivity and is matched with eight lanes of
PCIe 2.0 5Gb/s performance. The low-profile design of the SAS HBA includes a full-height bracket and a low-profile
mounting bracket that creates a universal fit for any server. The LSI SAS 9200-8e HBA is based on the
Fusion-MPT™-architected LSI SAS 2008 controller that integrates the latest enhancements in PCIe 2.0 technology and
6Gb/s SAS technology.
The LSI SAS 9200-8e HBA has onboard Flash memory for the firmware and BIOS.
2
HBA Features
The LSI SAS 9200-8e HBA features has the following features:
Implements one LSI SAS 2008 eight-port 6Gb/s to PCIe 2.0 controller
Supports eight-lane, full-duplex PCIe 2.0 performance
Supports eight external 6Gb/s SATA+SAS ports
Supports SATA and SAS link rates of 1.5Gb/s, 3.0Gb/s, and 6.0Gb/s
Provides two x4 external mini-SAS connectors (SFF-8088)
Supports passive cable
Supports up to 512 SATA or SAS end devices
Offers a full-height bracket and low-profile bracket
Provides multiple activity LEDs
Provides a universal asynchronous receiver/transmitter (UART) debug/diagnostic port
3
Functional Descriptions
3.1
PCIe
PCIe is a high-speed standard local bus for point-to-point interfacing of I/O components to the processor and the
memory subsystems in a high-end personal computer (PC). The LSI SAS 2008 controller chip contains the PCIe
functionality for the LSI SAS 9200-8e HBA. The LSI SAS 2008 controller chip connects directly to the PCIe bus and
generates timing and protocol in compliance with the PCIe specifications.