Sundance SMT329 - Manual (Page 34)

The status3 register is accessible by the VME host at address
IO base + 0x98-0x9B. The bit definitions for this register are:
31-28 30-16 15-12 28
Txrdcount Txwrcount
R, 0000 R, 0 R, 0000 R, 0
Bit Mnemonic Description
Txrdcount Transmit fifo read pointer
Txwrcount Transmit fifo write pointer
This status register is intended for diagnostic use only.
4.5.2 Reset (RST) register
This special control register is accessed in VME A32 IO space as either D16 or D32. It can be
accessed as D16 at address:
IO base + 0xC2
It can be accessed as D32 at address:
IO base + 0xC0
Only bit-4 is defined, and if this bit is set by the VME host, it causes all TIM sites, comm-port
buffers, and other motherboard logic to become reset. The board remains in such a state until
this bit is cleared by the VME host. This reset is the same bit as defined in VME Master
Status and Control register bit-0.
Note that a board reset clears the “A32 enable” bit in the VME Master Status and Control
register, which means this I/O Reset register is no longer available to the VME bus. For this
reason it is recommended that the board reset (bit 0) in the VME Master Status and Control
register is used to reset the board, as this register is always available.
4.5.3 Flash control interface
The AMD/Spansion S29GL256N10TFIR10 32M byte flash stores the connectivity bit map for
the Spartan3 comms port cross bar switch and the logic configuration data for both the
Virtex4 and the Spartan3.
The flash can be controlled by either the CPLD or the Virtex4. The flash data bus is connected
to the CPLD, the Virtex4 and the Spartan3. Following power on, the CPLD performs the
following:
User Manual SMT329 Page 34 of 52 Last Edited: 09/02/2007 10:58:00