Sundance SMT329 - Manual (Page 29)

4.4.4 TIM Global bus interface to the I/O registers
This address space occupies global bus addresses in the following region:
0xC000 0000 to 0xC0FF FFFF.
Individual I/O register addresses are detailed in the following table:
Area VME offset TIM address Peripheral Read/Write
FLASH D0-D3 C000 0100 Flash data Read/Write
FLASH D4-D7 C000 0101 Flash address Read/Write
FLASH D8-DB C000 0102 Flash Key Read/Write
FLASH DC-DF C000 0103 SP3 diagnostic Read/Write
CONTROL E0-E3 C000 0000 Control 1 Read/Write
CONTROL E4-E7 C000 0001 Control 2 Read/Write
CONTROL E8-EB C000 0002 Control 3 Read/Write
CONTROL EC-EF C000 0003 Control 4 Read/Write
CONTROL F0-F3 C000 0004 Status 1 Read
CONTROL F4-F7 C000 0005 Control 6 Read/Write
CONTROL F8-FB C000 0006 Control 7 Read/Write
CONTROL FC-FF C000 0007 Reserved -
I/O2 100-3FF C000 0200-
C000 02FF
DMA & RSL Read/Write
Actual DMA and RSL addresses in the IO2 space will be defined in a subsequent release of
this manual and Virtex4 configuration.
4.4.5 TIM Global bus interface to the VME bus master
This address space occupies global bus addresses in the following region:
0xC100 0000 to 0xC13F FFFF.
A global bus cycle in this address space causes a corresponding VME bus cycle. The VME
master takes the global bus address and shifts it left 2 bits to create a byte address. Bits 23-2
of this byte address are mapped directly to the VME bus address. It then takes the 8 bit VME
high address in Control register 4 to generate VME address bits 31-24, and the VME A1 bit in
Control register 4 is mapped to VME bus address A1. The following table details this process:
User Manual SMT329 Page 29 of 52 Last Edited: 09/02/2007 10:58:00