Sundance SMT329 - Manual (Page 31)

4.5 I/O Registers
The I/O registers are divided into 4 groups: Comm, RST, Flash, Control.
4.5.1 Comm Port Interface
Each TIM module has up to 6 byte-wide communications ports. Following a reset, 3 of these
comm ports are in output mode, and the other 3 are in input mode. The Virtex4 has 2 comm
ports which reset to output. TIM sites (1 to 4) have six numbered comm ports: Ports 0 to 2
are reset to output, and 3 to 5 are reset to input.
The Virtex4 Comm Port interface provides a route by which a VME host can talk to a TIM
comm-port, using a byte wide bi-directional parallel data bus and 4 handshake signals. Both
D16 and D32 accesses are allowed. This logic and associated circuitry includes fifo buffering
on reads and writes. The Virtex4 reset to out comm ports which are connected to this
interface can be switched to any TIM reset to in comm port through the comm port switch.
There are 2 comm port channels (VXS0 & VXS1) from the Virtex4 to the comm port switch.
The switch can connect each of these 2 channels to a different reset to in port on a TIM. Note
that there is only 1 VME comm port interface, and that a software controlled switch allows
dynamic switching of the VME comm port interface between VXS0 and VXS1.
All registers are 32 bits wide. The following address / register map is used:
VME
IO base
offset
address Register Read
Writ
e
Description
80-83 Comm port Data R/W Data I/O port
84-87 Comm port Data R/W Data I/O port
90-93 Comm port Status1 R General status
94-97 Comm port Status2 R Receive fifo status
98-9B Comm port Status3 R Transmit fifo status
9C-9F Reserved - -
There is only one comm port interface, and its data register is accessible at both addresses
indicated in the table above.
4.5.1.1 Comm Port Data register
The comm port data register is accessible as a D16 resource by first writing the upper data
bits (31 to 16) to address
IO base + 0x84-0x85,
User Manual SMT329 Page 31 of 52 Last Edited: 09/02/2007 10:58:00