Sundance SMT329 - Manual (Page 25)

Note that a VME bus error is generated by the VME slot 0 controller after a timeout period,
not by the SMT329.
The SMT329 can be reset at any time by the VME controller setting bit 0. As this bit is itself
cleared by a board reset, it will always read as 0.
The Ready bit is driven by the TIM config signal which indicates when all TIMs are ready
following a reset.
4.4.1.4 VME Sram Base Address Register (address 06-07)
This 16-bit register defines the base address of the sram for A32 addressing modes. The most
significant 9 bits of this register (D15-7) are compared to VME address signals A31-23. VME
address signals A22-A1 decode bytes in the 8M byte SRAM. The least significant 7 bits of this
register are not used.
4.4.1.5 VME I/O Base Address Register (address 08-09)
This 16-bit register is used to set the base address (in 256 byte blocks) of the I/O address
space.
This 16 bit base address is compared to the incoming A32 address bits A23-8, while bits A31-
24 are compared to FF hex. A match decodes a 256 byte space which is further decoded to
access the various devices in the I/O address space.
The 256 byte space is functionally equivalent to the I/O space in the SMT328. This space can
be expanded in the SMT329 by 768 bytes to a total size of 1024 bytes. This expansion is
software enabled, to maintain backwards compatibility. When the full 1024 byte space is
enabled, bits 0 and 1 of this VME I/O base address register are ignored.
4.4.1.6 VME Virtex 4 code revision
This 16 bit read only register reports the current revision of Virtex4 FPGA code.
4.4.1.7 VME Sub-class Register (1E)
The bit definitions for this 16-bit read only register are given below:
The bit definitions for this register are:
15 14-12 11-0
Sub class ID3
R, 0 R, 001 R, 0000 0111 1011
Always reads as 107B hex.
User Manual SMT329 Page 25 of 52 Last Edited: 09/02/2007 10:58:00