Sundance SMT329 - Manual (Page 33)

Rxalfull Receive fifo almost full (has 128 empty entries)
Rxemp Receive fifo is empty
Rxfull Receive fifo is full
Rxrderr Receive fifo read while fifo empty
Rxwrerr Receive fifo write while fifo full
Txalemp Transmit fifo almost empty (has 128 entries left)
Txalfull Transmit fifo almost full (has 128 empty entries)
Txemp Transmit fifo is empty
Txfull Transmit fifo is full
Txrderr Transmit fifo read while fifo empty
Txwrerr Transmit fifo write while fifo full
The receive fifo not empty bit (-Rxemp) becomes set when a receive word is in the comm port
data receive fifo. When all the comm port data in the receive fifo is read, this bit is reset.
When the transmit fifo not full bit (-Txfull) is set, it indicates that the VME host can write a
new 32 bit word to the comm port data register for later transmission to the comm port.
4.5.1.3 Comm Port Status2 register
The status2 register is accessible by the VME host at address
IO base + 0x94-0x97. The bit definitions for this register are:
31-28 30-16 15-12 28
Rxrdcount Rxwrcount
R, 0000 R, 0 R, 0000 R, 0
Bit Mnemonic Description
Rxrdcount Receive fifo read pointer
Rxwrcount Receive fifo write pointer
This status register is intended for diagnostic use only.
4.5.1.4 Comm Port Status3 register
User Manual SMT329 Page 33 of 52 Last Edited: 09/02/2007 10:58:00