Sundance SMT329 - Manual (Page 28)

The sram is organised to allow the VME bus master to perform D8, D16, D32 or D64 cycles,
and word swapping buffers are included for this purpose. Transfers can be single, or burst
using either 2eVME or 2eSSTT. This address space occupies 8M bytes, and has a base
address set by the VME controller in the VME configuration register “SRAM Base Address”.
This address space is decoded in the VME A32 space, which means that the VME address
modifiers must be set to either of the following:
Hex Code VME
space
Function
0D A32 Extended supervisory data access
09 A32 Extended non privileged data access
The VME address bits are decoded as follows:
VME Address
bit Compare to Comment
31-23 SRAM Base
D15-7
SRAM Base is programmed by the VME controller
22-0 - Select byte address in the 8M byte SRAM
The VME interface to the SRAM supports byte write.
User Manual SMT329 Page 28 of 52 Last Edited: 09/02/2007 10:58:00