Sundance SMT399-160 - Manual (Page 30)

5.4.27 DDS0 Register – 0x1A – RAM Segment Control Word
3.
For more details, refer to AD9954 datasheet.
DDS0 Register – 0x1A – RAM Segment Control Word 3
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 RAM Segment 3 Final Address[7:0]
Default ‘00000000’
1 RAM Segment 3 Address Ramp Rate[15:8]
Default ‘00000000’
5.4.28 DDS0 Register – 0x1B – RAM Segment Control Word
3.
For more details, refer to AD9954 datasheet.
DDS0 Register – 0x1B – RAM Segment Control Word 3
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 RAM Segment 3 Address Ramp Rate[7:0]
Default ‘00000000’
1 Not Used
Default ‘00000000’
5.4.29 DDS0 Register – 0x1C – Falling Delta Frequency
Tuning.
For more details, refer to AD9954 datasheet.
DDS0 Register – 0x1C – Falling Delta Frequency Word
Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 Falling Delta Frequency Word[7:0]
Default ‘00000000’
1 Falling Delta Frequency Word[15:8]
Default ‘00000000’
DDS0 Register – 0x1C – Falling Delta Frequency Word
Setting Falling
Delta
Frequency
Word
Description
The Falling Delta Frequency word is a 32-bit register that is used in the sweeping mode.
User Manual SMT399-160 Page 30 of 39 Last Edited: 24/05/2007 17:12:00