Sundance SMT399-160 - Manual (Page 15)

0x11 DDS0 – Register B (0xB) – RAM Segment Control
Word 0. Read-back (FPGA Register) DDS0 – Register B (0xB).
0x12 DDS0 – Register C (0xC) – RAM Segment Control
Word 0. Read-back (FPGA Register) DDS0 – Register C (0xC).
0x13 DDS0 – Register D (0xD) – RAM Segment Control
Word 1. Read-back (FPGA Register) DDS0 – Register D (0xD).
0x14 DDS0 – Register E (0xE) – RAM Segment Control
Word 1. Read-back (FPGA Register) DDS0 – Register E (0xE).
0x15 DDS0 – Register F (0xF) – RAM Segment Control
Word 1. Read-back (FPGA Register) DDS0 – Register F (0xF).
0x16 DDS0 – Register 10 (0x10) – RAM Segment Control
Word 2. Read-back (FPGA Register) DDS0 – Register 10
(0x10).
0x17 DDS0 – Register 11 (0x11) – RAM Segment Control
Word 2. Read-back (FPGA Register) DDS0 – Register 11 (0x11).
0x18 DDS0 – Register 12 (0x12) – RAM Segment Control
Word 2. Read-back (FPGA Register) DDS0 – Register 12 (0x12).
0x19 DDS0 – Register 13 (0x13) – RAM Segment Control
Word 3. Read-back (FPGA Register) DDS0 – Register 13 (0x13).
0x1A DDS0 – Register 14 (0x1A) – RAM Segment Control
Word 3. Read-back (FPGA Register) DDS0 – Register 14 (0x14).
0x1B DDS0 – Register 15 (0x1B) – RAM Segment Control
Word 3. Read-back (FPGA Register) DDS0 – Register 15 (0x15).
0x1C DDS0 – Register 16 (0x1C) – Falling Delta Frequency
Tuning Word. Read-back (FPGA Register) DDS0 - Falling Delta
Frequency Tuning Word.
0x1D DDS0 – Register 17 (0x1D) – Falling Delta Frequency
Tuning Word. Read-back (FPGA Register) DDS0 - Falling Delta
Frequency Tuning Word.
0x1E DDS0 – Register 18 (0x1E) – Falling Sweep Ramp rate
Word. Read-back (FPGA Register) DDS0 - Falling Sweep
Ramp rate Word.
0x1F DDS0 – Register 19 (0x1F) – Rising Delta Frequency
Tuning Word. Read-back (FPGA Register) DDS0 - Rising Delta
Frequency Tuning Word.
0x20 DDS0 – Register 20 (0x20) – Rising Delta Frequency
Tuning Word. Read-back (FPGA Register) DDS0 - Rising Delta
Frequency Tuning Word.
0x21 DDS0 – Register 21 (0x21) – Rising Sweep Ramp rate
Word. Read-back (FPGA Register) DDS0 - Rising Sweep
Ramp rate Word.
0x26 DDS1 – Register 0 (0x0) – Control Function Register. Read-back (FPGA Register) DDS1 – Register 0 (0x0).
0x27 DDS1 – Register 1 (0x1) – Control Function Register. Read-back (FPGA Register) DDS1 – Register 1 (0x1).
0x28 DDS1 – Register 2 (0x2) – Control Function Register. Read-back (FPGA Register) DDS1 – Register 2 (0x2).
0x29 DDS1 – Register 3 (0x3) – Amplitude Scale Factor
Register. Read-back (FPGA Register) DDS1 – Register 3 (0x3).
0x2A DDS1 – Register 4 (0x4) – Amplitude Ramp Rate
Register. Read-back (FPGA Register) DDS1 – Register 4 (0x4).
0x2B DDS1 – Register 5 (0x5) – Frequency Tuning Word 0. Read-back (FPGA Register) DDS1 – Register 5 (0x5).
0x2C DDS1 – Register 6 (0x6) – Frequency Tuning Word 0. Read-back (FPGA Register) DDS1 – Register 6 (0x6).
0x2D DDS1 – Register 7 (0x7) – Phase Offset Word. Read-back (FPGA Register) DDS1 – Register 7 (0x7).
0x2E DDS1 – Register 8 (0x8) – Frequency Tuning Word 1. Read-back (FPGA Register) DDS1 – Register 8 (0x8).
0x2F DDS1 – Register 9 (0x9) – Frequency Tuning Word 1. Read-back (FPGA Register) DDS1 – Register 9 (0x9).
0x30 DDS1 – Register A (0xA) – RAM Segment Control
Word 0.
Read-back (FPGA Register) DDS1 – Register A (0xA).
0x31 DDS1 – Register B (0xB) – RAM Segment Control
Word 0. Read-back (FPGA Register) DDS1 – Register B (0xB).
0x32 DDS1 – Register C (0xC) – RAM Segment Control
Word 0. Read-back (FPGA Register) DDS1 – Register C (0xC).
0x33 DDS1 – Register D (0xD) – RAM Segment Control Read-back (FPGA Register) DDS1 – Register D (0xD).
User Manual SMT399-160 Page 15 of 39 Last Edited: 24/05/2007 17:12:00