Sundance SMT377 - Manual (Page 17)

Version 1.1 Page 17 of 22 SMT377 User Manual
Getting control of the SMT377.
The SMT377 once configured needs to receive control words via CommPort 3 to start
converting digital data into analogue.
The board consists of 8 DAC channels. Each channel is interfaced with one FIFO
all implemented in the Virtex-II FPGA. It allows compensating speed changes
between the receiving and transmitting part. The programmable device slows down
automatically the transfer when necessary.
The eight channels are independent in terms of data. A digital data can be sent at
anytime to any of the eight channels or to four or eight channels at a time, by loading
a control word into the internal control register.
The SMT377 includes two Sample Rate Generators (SRGs), which can be loaded
independently at anytime, by sending a control word to the internal register. The first
SRG deals with Channel 1, 2, 3 and 4 and the second one with Channels 5, 6, 7 and
8.
The control register also allows the users to write/read into/from the on-board
ZBTRAM memory. Each memory address points on a 16-bit sample. Writing is
always made in burst mode, i.e. a Start Address is loaded first, then a burst size and
then data are sent one by one. Data can then be read back and either be sent back
to the host or to the DACs as samples, which makes it behaving as a pattern
generator.
Internal registers can be reset via the control register.
All these functions are detailed in the following table: