Sundance SMT365G - Manual (Page 8)

Version 1.0.0 Page 8 of 23 SMT365G User Manual
TMS320C6416T
The processor will run with zero wait states from internal SRAM.
An on-board crystal oscillator provides the clock used for the C60 which then
multiplies this by 12 internally.
Boot Mode
The SMT365G can be configured to use one of two boot modes after a reset. These
are HPI (host port interface) and Flash.
Flash Boot
1. The processor copies a bootstrap program from the first part of the flash
memory into internal program RAM starting at address 0.
2. Execution starts at address 0.
The standard bootstrap supplied with the SMT365G then performs the following
operations:
1. All relevant C60 internal registers are set to default values;
2. The FPGA is configured from data held in flash memory and sets up the
communication ports, the global bus and the Sundance High-speed Buses.
This step must have been completed before data can be sent to the comm-
ports from external sources such as the host or other TIMs;
3. A C4x-style boot loader is executed. This will continually examine the six
communication ports until data appears on one of them. The bootstrap will
then load a program in boot format from that port; the loader will not read data
arriving on other ports.
4. Finally, control is passed to the loaded program.
The delay between the release of the board reset and the FPGA configuration is
around 1s for a SMT365G (600MHz clock).
A typical time to wait after releasing the board reset should be in excess of this
delay, but no damage will result if any of the I/Os are used before they are fully
configured. In fact, the comm. Ports will just produce a not ready signal when data
transfer is attempted during this time, and then continue normally after the FPGA
is configured.
HPI Boot
The C60’s HPI (16 bit data interface) is connected directly to the FPGA. This
mode is therefore only used by custom FPGA configurations.