Sundance SMT365G - Manual (Page 10)

Version 1.0.0 Page 10 of 23 SMT365G User Manual
ZBTRAM
Memory space CE0 is used to access 8MB of ZBTRAM over EMIFA. The ZBTRAM
operates at the external oscillator frequency of 133MHz.
The EMIFA CE0 memory space control register should be programmed with the
value 0x000000E0.
Note that the DSP only has 20 address pins on the EMIFA and cannot therefore
directly address more than 8Mbytes of SRAM (the ZBTRAM is a type of SRAM with
non-multiplexed address pins).
FLASH
An 8MByte Flash ROM device is connected to the C60 EMIFB.
The ROM holds boot code for the C60, configuration data for the FPGA, and optional
user-defined code.
The EMIFB CE1 and CE2 space control registers should be programmed with the
value 0xFFFFFF03.
As the C60 only provides 20 address lines on its EMIFB, both CE1 & CE2 are used
to access this device. This in itself allows the direct access of 4Mbytes. A paging
mechanism is used to select which half of the 8M device is visible in this 4Mbyte
window.
As the EMIFB CE1 & 2 memory spaces alias throughout the available range, the
flash device can be accessed using the address range 0x67E00000-0x681FFFFF.
This gives a 4Mbyte continuous space.
The flash can be divided into the four logical sections shown in the following figure
(paging bit is bit 21).
Page0
(2 MBytes)
Page1
(2 MBytes)
Page1
(2 MBytes)
0x67C00000
0x67E00000
0x68000000
0x68200000
0x68400000
CE1
CE2
Page0
(2 MBytes)
Section 1
Section 2
Section 3
Section 4
Figure 1: Flash logical sections
To change the state of the page bit, you need to write to the following address as
shown (the data written is irrelevant):