Sundance SMT365G - Manual (Page 11)

Version 1.0.0 Page 11 of 23 SMT365G User Manual
Address Flash page selected
0x6C000000 Page 0 (1 st and 3r d
sections enabled)
0x6C000001 Page 1 (2 nd and 4 th
sections enabled)
The EMIFB CE3 space control register should be programmed with the value
0xFFFFFF03.
This mechanism is identical in operation to that needed for the largest ZBTRAMs.
Virtex FPGA
The SMT365G incorporates a Xilinx Virtex XC2V1000 FPGA. This device controls
the majority of the I/O functionality on the module, including the comm ports, SHBs
and global bus.
This device requires configuring after power-up (the Virtex technology is an SRAM
based logic array). This configuration is performed by the DSP as part of the boot
process.
Two control register bits are needed for this purpose, one to put the FPGA into a
‘waiting for configuration’ state, and another to actually transfer the configuration
data.
The PROG pin (causes the FPGA to enter the non-configured state) is accessed at
address 0x6C02000X. Writing to address 0x6C020000 will assert this pin, and
address 0x6C0200001 will de-assert this pin.
The configuration data clock is accessed at address 0x6C080001. Each bit of the
FPGA’s configuration bit-stream must be serially clocked through this address.
Note: This configuration process is part of the standard boot code, and does not
need to be implemented in any user application.