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Sundance SMT358 User Manual

Page 19

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Version 2.5

Page 19 of 25

SMT358 User Manual

The design makes use of a Comm-port to pass the reconfigure command to the
SMT358 FPGA and waits for a 1 on the LSB of this Comm-Port.

If another Comm-port than Comm-port 3 is used, the pins corresponding to Comm-
port 3 on the FPGA must be tied to “1” in the FPGA (As designed in the
reconfiguration example design)

The following description is referring to Figure 8.

6) The FPGA reads the command and then warns the CPLD by sending an interrupt

(FPGARESET low) that it decoded a reconfigure command. The FPGA goes into
a RESET state and leaves Comm-port 3 available for the CPLD. (in case Comm-
port3 is used by the design).

7) On receiving the FPGARESET interrupt, the CPLD goes into the WAITCMD State

and polls Comm-port 3 for a keyword. (0xBCBCBCBC or 0xBCBCBC00)

8) On receiving the keyword,

If it is the end-of-bitstream keyword 0xBCBCBC00, the FPGA DOES NOT get

reconfigured, the CPLD leaves Comm-port 3 available for the FPGA and
enters into an IDLE state to wait for the next interrupt.

If it is the start-of-bitstream keyword 0xBCBCBCBC, repeat step 2 to 3).

Software tools

The SMT6358 is a suite of software support for the SMT358.

It contains:

A library of IP cores: a Comm-port Interface, an SDB interface and a ZBT

Controller.

Design examples of Comm-Port, SDB and memory applications.

The pin allocation file for the Virtex/E: VIRTEX_TOP.ucf.

2 conversion softwares needed AFTER a bitstream has been generated to

download it in the SMT358 FPGA.

Some additional software is required:

A CAD platform to create a schematic or VHDL design.

A simulator to simulate the hardware designs.

Xilinx Place & Route software such as M3.3i.

Texas Instrument C compiler or 3L parallel C compiler.