Sundance SMT358 - Manual (Page 14)

Version 2.5 Page 14 of 25 SMT358 User Manual
FPGA
The FPGA is to be configured over Comm-Port 3 via the CPLD. The configuration bitstream
is sent by a host, a ‘C6x or ‘C4x processor. This feature will allow a system to dynamically
change the FPGA firmware. The configuration LED indicates that configuration is complete.
The FPGA drives 4 LEDs, and is connected to it’s own local oscillator package.
The FPGA firmware will be user defined, and can be done on demand.
Typical functions that can be implemented in the FPGA are:
• Full bi-directional global-bus interface
• Full bi-directional Comm-Port interface
• Bi-directional SDB Interface
• RAM, FIFOs, Dual port RAMs up to a total of 16K Bytes
• Communication protocols
• DSP pre-processors
• Any digital function that will fit in this size device
The SMT358 TIM can typically be used to interface with a SMT338 Frame Grabber over the
SDB connectors. The SMT358 can then perform customer specific data formatting before
sending it to a nearby DSP TIM via Comm-Port or SDB.
Due to the parallel nature of an FPGA it is well suited to handle multiple high-speed I/O lines.
The FPGA can then provide a cleaner bus-interface to the associated DSP processors.