Sundance SMT358 - Manual (Page 17)

Version 2.5 Page 17 of 25 SMT358 User Manual
2) On receiving the start-of-bitstream keyword 0xBCBCBCBC, The CPLD reads out
the FPGA bitstream from Comm-Port 3 and configures the FPGA (CONFIG
State).
3) The FPGA releases its DONE pin when the configuration phase is finished. At
this time LED1 goes on (LED1 is directly driven by DONE). Then, the FPGA
completes its startup sequence and the design downloaded is now ready to start.
• If the design inside the FPGA instantiates Comm-Port 3: it must be kept reset
while the bitstream finishes to be downloaded. To do so, use the
FPGARESET pin as a global reset for the Comm-Port interface in particular
and for the whole design in general. FPGARESET is a bi-directional active low
signal. The CPLD asserts FPGARESET low until it receives the end-of-
bitstream word BCBCBC00 defining the end of the configuration process and
enters an IDLE State waiting for an interrupt (general TISRESET from the PCI
or FPGARESET coming from the FPGA this time).
• If the design inside the FPGA doesn’t instantiate Comm-Port 3: The CPLD
asserts FPGARESET low until it receives the end-of-bitstream word
0xBCBCBC00 defining the end of the configuration process and enters an
IDLE State waiting for an interrupt (general TISRESET from the PCI or
FPGARESET from the FPGA). Meanwhile, the FPGA design can start if it
doesn’t use FPGARESET as a global reset. (but a good practice is to use
FPGARESET as a global reset).
Figure 7: Global Reset routing. Use of FPGARESET as a global reset for designs.
FPGA
XCVxxxxxBG560
Configuration Logic CPLD
Config Control
Top Primary
Connector
Com-Port 3
Com-Port 3 Ctrl Com-Port 3 Data
Config D[7:0]
TIS_RESET
FPGARESET
TIS_RESET
FPGARESET
Logic
OR
TIS_RESET