Sundance SMT118 - Manual (Page 8)

Version 1.0 Page 8 of 20 SMT118v2 User Manual
Flash
A 16M bit flash memory is provided and can be accessed through the FPGA. This
device can be accessed in either 8-bit or 32-bit mode determined by the setting of a
control register. When accessed as a 32-bit word, 15 wait states should be inserted.
These wait states are determined by the CPU TIM. For operation with a ‘C4x TIM,
only 7 wait states need be inserted. For the setting of wait states please consult the
respective documentation for the CPU module being used.
The flash memory global address is fixed at 0xF8000000. These addresses, as are
all global addresses, are for 32-bit data. If the flash is set to word mode then all 32
bits of data are valid. If set to byte mode then only the lower 8 bits of the data word
will contain valid data.
The control register for changing the flash mode is provided at address 0xFC000000.
Setting bit 0 of this register will enable word mode.
The flash device cannot be written to when in word mode.
TTL
Twenty-four TTL I/O signals are available via the CONN3 connector. Each signal can
be set as either an input or output independently of any other signal. The direction of
these signals is controlled by the TTL direction control register at address
0xFA800000. Each of the 24 least significant bits within this register is associated
with the direction of the corresponding TTL I/O signal. Setting a bit to logic 1 will
enable that I/O as an output. After a reset, all I/O direction is set to input.
These signals are at LVTTL signal levels. They will drive a normal TTL input (V out
min of 2.4V), although the use of LVTTL inputs is suggested, they can withstand a 5V
input (an absolute maximum of 5.5V and minimum of –0.5V must be ensured).
The output state is controlled by writing to the register at address 0xFA000000, and
the input state is determined by reading from this register.
The TTL section of the FPGA can provide an interrupt source when any of the inputs
changes state. These inputs are sampled using a 60MHz clock, and so for a change
to be recognised, the new state must last longer than 15ns. This input change status
bit is cleared when the TTL data register is read (address 0xFA000000).