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Sundance SMT118 User Manual

Page 11

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Version 1.0

Page 11 of 20

SMT118v2 User Manual

The state of all possible interrupt sources can be determined by reading the interrupt
status register (ISR) at address 0xFF000000.
The bit definitions are shown here:

Bit Function

0 CPU,

IIOF

0

1 CPU,

IIOF

1

2 CPU,

IIOF

2

3 CPU,

NMI

4

I/O Site 1, IIOF 0

5

I/O Site 1, IIOF 1

6

I/O Site 1, IIOF 2

7

I/O Site 1, NMI

8

I/O Site 2, IIOF 0

9

I/O Site 2, IIOF 1

10

I/O Site 2, IIOF 2

11

I/O Site 2, NMI

12 UART

RXRDY

13 UART

TXRDY

14

User link 0

15

User link 1


All bits are active low.

See also other documents in the category Sundance Equipment: