Sundance SMT118 - Manual (Page 10)

Version 1.0 Page 10 of 20 SMT118v2 User Manual
Interrupts
Each of the four possible interrupt signal inputs to the CPU TIM (IIOF0-2 & NMI) can
be configured to generate an interrupt on any combination of the following sources:
I/O site 1 IIOF0-2, I/O site 1 NMI, I/O site 2 IIOF0-2, I/O site 2 NMI, QUART or TTL
input change.
Each of the CPU’s interrupt input signals has an independent interrupt control
register (ICR). These are accessed at addresses 0xFD000000 to 0xFD000003. The
following table shows the bit positions to set to enable the various sources:
Bit Interrupt source
0 SITE 1 IIOF0
1 SITE 1 IIOF1
2 SITE 1 IIOF2
3 SITE 1 NMI
4 SITE 2 IIOF0
5 SITE 2 IIOF1
6 SITE 2 IIOF2
7 SITE 2 NMI
8 QUART IRQ
9 TTL input change
Setting the corresponding bit(s) will enable that interrupt source.