Sundance SMT118 - Manual (Page 6)

Version 1.0 Page 6 of 20 SMT118v2 User Manual
TIM sites
The SMT118 has three TIM sites. Only the primary or CPU site can be considered to
be 100% TIM standard compliant. The two I/O sites are compliant with the exception
of the optional global bus connector.
JTAG
The JTAG chain includes all three TIM sites with the proviso that there must always
be a CPU module in SITE 1.
A standard 14-pin XDS510 compatible header (CONN9) is provided to allow
debugging.
In addition to the TI standard 14-pin JTAG header, there is a 20 way 0.050” pitch
high-density connector which allows direct JTAG connection to the
SMT310 series of
PCI TIM motherboards with embedded test bus controller.
Global Bus
The global bus connectors are essentially all wired in a common bus. This includes
the control signals, address and data buses. With this connectivity on the control
signals, it is evident that only the CPU site is able to generate global bus ‘master’
cycles. The two I/O sites are termed ‘slaves’, and they can contain memory mapped
resources which respond to the CPU global bus cycles.
It is not possible to insert a CPU TIM into the I/O sites unless the CPU TIM does not
have the optional global bus connector or, that the SMT118 has been specifically
modified at build time to remove these global bus connectors from the I/O sites.
CPU
The CPU TIM site connects the global bus address, data and control signals directly
to the other I/O sites’ global bus connectors.
These signals are also connected to an FPGA on the carrier board which is used to
provide the main features of this board.
Interrupts are provided via the FPGA onto the TIM IIOF and NMI signals. These
signals are inputs only to the CPU site.
I/O
The I/O sites receive the global bus address bus and control signals. They cannot
initiate a global bus cycle independently.
The four interrupt sources from each of these modules are routed to the FPGA (a
total of 8 separate interrupts).
Each I/O site has separate connectors to allow serial communication between one
another, and also to allow communication to a latching connector on the carrier
board. This provision was specifically designed for the SMT366 module and allows
the sharing of sampling clocks and outputting of DAC analog signals. There is no