Sensoray 421 - Manual (Page 7)

Sensoray Model 421 Instruction Manual Page 5
Encoder Interface
Three counter channels reside on the 421. Each
channel is optimized for incremental encoders by
providing the following elements:
— Input buffers - interfaces to TTL, CMOS, or RS422 signals.
— Decode logic - detects and converts encoder edges into
clock and direction signals.
— 16-bit up/down counter - maintains encoder position
without resorting to multiple counter channels.
— Power - 5-volts is accessible to power encoders.
Additional logic is incorporated to implement
synchronous transfer of encoder counts into a 16-bit
holding register. This feature assures error-free
acquisition of encoder counts by the ISAbus master.
Phase Inputs
Each counter channel has two input signals, called
the “A” and “B” phases. Depending on the
application, one or both of these signals may be
connected to an encoder.
If both input phases are used, the phases are assumed
to be Quadrature encoded, meaning that they are 90
degrees out of phase with each other. Counter
channels will count both up and down by decoding
the timing relationship of the two phase inputs.
If only one phase input is used, the input is said to be
Single-phase. In this case, counter channels will
count either up or down, but not both. This
configuration is typically used to count pulses from
non-encoder devices that produce a single clock
output.
Quadrature encoded inputs have advantages over
single-phase inputs. Counters will not accumulate
errors when an encoder changes direction or dithers
about a state transition boundary. Also, it is possible
to increase the effective resolution of an encoder by
clocking the counters at a multiple of the single-
phase clock rate.
Mode Selection
Counter channels may be configured for any of eight
operating modes. A mode register is provided to
select the operating mode of the three counter
channels. All channels must be configured for the
same operating mode.
By selecting a counter mode, you are specifying a
combination of counter input type (quadrature
encoded or single-phase), clock multiplier (times 1, 2
or 4), and count direction (normal or reverse).
421 Reset
Hardware or software reset of the 421 will
asynchronously zero all three encoder counters, the
counter mode register (thereby selecting counter
operational mode 0) and the 16-bit data holding
register. Channel logic is re-enabled for counting
upon termination of the reset pulse.
Rollover
All encoder counters will increment from FFFF to
0000 when counting up, and will decrement from
0000 to FFFF when counting down.
No interrupts or status flags are available to notify
the ISAbus master of a rollover event. The master
should read encoder position data with sufficient
frequency to guarantee the validity of position data.
Input Buffer
w/Hysterisis Decode
Logic Up/Down
Counter
D
A
T
A
S
E
L
E
C
T
O
R
Input Buffer
w/Hysterisis Decode
Logic Up/Down
Counter
Input Buffer
w/Hysterisis Decode
Logic Up/Down
Counter
Timing &
Control
16-bit Data
Register
Encoder
Inputs
Data to
ISAbus
Host
Encoder Interface Block Diagram