Sensoray 421 - Manual (Page 6)

Page 4 Sensoray Model 421 Instruction Manual
Reset
Watchdog Timer
The 421 may be reset by either a “hard reset” from
the ISAbus system reset signal or a “soft reset” under
software control of the ISAbus master.
Soft Reset
A “soft reset” may be performed at any time. This
causes a local reset on only the 421 and will not reset
any other devices on the ISAbus. A soft reset is
invoked by writing to the RESET port.
RESET (11):
The value written to the RESET port is ignored, but
should be all zeros for compatibility with future
product enhancements.
Default State Following a Reset
Both hard and soft resets force the 421 to the
following condition:
— The watchdog timer is disabled.
— All DAC outputs are disabled.
— All encoder counters are reset to zero.
— Encoder counters default to Mode 0.
— All relay channels are turned off.
0 0 0 0 0 0 0 0
Enabling/Disabling the Watchdog
The watchdog is enabled and disabled by writing to
the CHCTRL port at board base address + 12. The port
is structured as follows:
CHCTRL (12):
Set W to logic one to enable the watchdog or set to
zero to disable the watchdog. Note that D is used to
enable and disable DAC outputs. Make sure D is set
properly when changing the watchdog enable bit so
that you don’t inadvertently enable or disable the DAC
outputs.
Refreshing the Watchdog
The watchdog is refreshed by writing to the HITDOG
port. The data value written to this port is ignored by
the 421, but should be all zeros for compatibility with
future product enhancements.
HITDOG (15):
Routing the Watchdog to the ISAbus
A watchdog timeout may be used to generate a system
reset. Two-pin connector P1 may be connected — via
user-supplied two-conductor cable — to your ISAbus
active-low external reset input.
You may leave connector P1 disconnected if you will
not be using the watchdog function.
0 0 0 0 1 0 D W
0 0 0 0 0 0 0 0
Embedded systems often include a watchdog
timer to regain program control following an
unplanned loss of control by the ISAbus master.
In such systems, the CPU is responsible for
periodically refreshing the watchdog timer to
prevent a timeout. Should the CPU crash, the
watchdog will not be refreshed and will
eventually timeout. The resulting timeout will
restart the CPU.
The 421 watchdog timer has a guaranteed
minimum timeout of 630 milliseconds.
Consequently, the interval between any two timer
refreshes must not exceed 630 milliseconds.
Some CPU’s are not able to refresh the watchdog
at the mandatory minimum rate during system
boot or critical I/O operations. To accomodate
these situations, the 421 provides a control
register for enabling and disabling the watchdog
under program control.
The first watchdog refresh must occur no later
than 630 milliseconds after enabling the timer.
The watchdog is automatically disabled by a soft
reset or system-wide hard reset.