Sensoray 421 - Manual (Page 12)

Page 10 Sensoray Model 421 Instruction Manual
D/A Interface
.
DAC
DAC0LSB
8-bit Register
DAC0MSB
4-bit Register
12-bit
Output
Register
DAC Enable
Register
CMOS
Switch
E
0 to +10V
Output
Local
Data
Bus
G
DAC Channel 0
(1 of 4 channels shown)
LDAC
E
G DAC
Channel 1
E
G DAC
Channel 2
E
G DAC
Channel 3
D/A Subsystem Block Diagram
(DACEN)
DAC Enable Register
Each DAC channel consists of a low-byte/high-
nibble bus register pair, 12-bit output register, 12-bit
D/A converter, and CMOS switch.
All four CMOS switches are enabled by the one-bit
DAC Enable Register. When enabled, the CMOS
switches connect all four DAC outputs to 40-pin
header P2. When disabled, all DAC output signals at
P2 are pulled down to zero volts.
A control strobe — LDAC — simultaneously
transfers data from the four bus register pairs to their
corresponding 12-bit output registers. DAC output
ranges are fixed at 0 to +10 volts.
Following a reset, the four 12-bit DAC output
registers contain indeterminate values. To ensure
orderly startup, the DAC Enable Register (DACEN)
turns off all CMOS switches to prevent random DAC
voltages from reaching the analog I/O connector.
DACEN — which is automatically cleared by a reset
— may be manipulated by the ISAbus master. The
DACEN register is accessed through the write-only
CHCTRL port.
CHCTRL (12):
The D bit enables DAC outputs when set to 1 and
disables DAC outputs when set to 0.
Note: the W bit, which enables and disables the
watchdog timer, is also controlled by this port. Make
sure you don’t inadvertently change the watchdog
enable bit when enabling or disabling the DAC
outputs.
0 0 0 0 1 0 D W