Measurement Computing PPIO-AI08 - Manual (Page 10)

5 REGISTER ARCHITECTURE
5.1 INTRODUCTION
The PPIO-AI08 is controlled and monitored by writing and reading from three
consecutive 8-bit I/O registers.
The process of accessing the registers on the board is complicated by the fact that the
board registers are accessed through the parallel port registers. The PPIO-AI08 is
supported by the Universal Library. We recommend that you use this library rather
than attempt register level programming. If you have determined that it is necessary,
the information for low level programming follows:
5.2 PARALLEL PORT REGISTERS
As stated previously, access to the PPIO-AI08 registers is done through the PCs
parallel port. The parallel port has 8-bits of latched data, 4-bits of control outputs,
and 5-bits of status inputs. The 8-bit data port will be used for address or data to the
ppio. The control outputs will be used to command address latch, write data, read data
or initialize. 4 of the status inputs will be used as data input in 4-bit nibbles, plus an
interrupt signal.
Parallel port address usage:
BASE + 0: DATA TO PPIO (8-BIT)
BASE + 1: DATA FROM PPIO (4-BIT)
BASE + 2: CONTROL SIGNALS TO PPIO (RD, WR, ADDR, INIT)
5.2.1 Control Signals: (BASE + 2):
PIN BIT SIGNAL DESCRIPTION COMMON NAME
1 0 WRITE STROBE -STROBE
14 1 READ STROBE -AUTO LF
16 2 -INIT/ENABLE -INIT
17 3 ADDRESS STROBE -SLCT IN
4 IRQ EN (SW ONLY; ENABLES ACK TO IRQ7)
5 NA
6 NA
7 NA
6