Measurement Computing PCI-DIO48H/CTR15 - Manual (Page 12)

5.1 PCI-DIO48H/CTR15 REGISTER DESCRIPTION
INTERRUPT STATUS/CONTROL
BADR1 + 4Ch
READ/WRITE
INTE INTPOL INT x x x x x x
0 1 2 3 4 5 6 7 31:8
This register, as with all the 9052 registers, is 32 bits long. Since the rest of the
register has specific control functions, they must be masked off when accessing the
interrupt control functions.
INTE Interrupt Enable
0 = disabled
1 = enabled (default).
INTPOL Interrupt Polarity
0 = active low (default)
1 = active high.
INT Interrupt Status
0 = interrupt is not active
1 = interrupt is active.
The digital I/O ports emulate 8255, Mode 0 operation.
PORT 1A DATA
BADR2 + 00h
READ/WRITE
A0 A1 A2 A3 A4 A5 A6 A7
0 1 2 3 4 5 6 7
PORT 1B DATA
BADR2 + 01h
READ/WRITE
B0 B1 B2 B3 B4 B5 B6 B7
0 1 2 3 4 5 6 7
PORT 1C DATA
BADR2 + 02h
READ/WRITE
CL0 CL1 CL2 CL3 CH0 CH1 CH2 CH3
0 1 2 3 4 5 6 7
8