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Counters – Measurement Computing PCI-DAS1002 User Manual

Page 21

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PCI-DAS1002 User's Manual

Specifications

21

Counters

Table 9. Counter specifications

Parameter

Specification

Counter type

82C54

Configuration

Two 82C54 devices. 3 down counters per 82C54, 16 bits each

82C54A:

Counter 0 - ADC residual
sample counter

Source:

ADC Clock

Gate:

Internal programmable source

Output:

End-of-Acquisition interrupt

Counter 1 - ADC pacer lower
divider

Source:

10 MHz oscillator

Gate:

Tied to counter 2 gate, programmable source

Output:

Chained to counter 2 clock

Counter 2 - ADC pacer upper
divider

Source:

Counter 1 output

Gate:

Tied to counter 1 gate, programmable source

Output:

ADC pacer clock (if software selected). Available at
user connector.

82C54B:

Counter 0 - pretrigger mode

Source:

ADC clock

Gate:

External trigger

Output:

End-of-Acquisition interrupt

Counter 0 - user counter 4
(when in non-pretrigger mode)

Source:

User input at 100-pin connector (CTR4 CLK)
or internal 10 MHz (software selectable)

Gate:

User input at 100-pin connector (CTR4 GATE)

Output:

Available at 100-pin connector (CTR4 OUT)

Counter 1 - user counter 5

Source:

User input at 100-pin connector (CTR5 CLK)

Gate:

User input at 100-pin connector (CTR5 GATE)

Output:

Available at 100-pin connector (CTR5 OUT)

Counter 2 - user counter 6

Source:

User input at 100-pin connector (CTR6 CLK)

Gate:

User input at 100-pin connector (CTR6 GATE)

Output:

Available at 100-pin connector (CTR6 OUT)

Clock input frequency

10 MHz max

High pulse width (clock input)

30 ns min

Low pulse width (clock input)

50 ns min

Gate width high

50 ns min

Gate width low

50 ns min

Input low voltage

0.8 V max

Input high voltage

2.0 V min

Output low voltage

0.4 V max

Output high voltage

3.0 V min

Crystal oscillator frequency

10 MHz

Frequency accuracy

50 ppm