Measurement Computing CIO-DAS800 - Manual (Page 18)

Counter section
Counter type 82C54
Configuration 3 down-counters , 16 bit resolution
Counter 0 - independent user counter
Source: external, user connector (Counter 0 In)
Gate: external, user connector (Gate 0)
Output: user connector (Counter 0 Out)
Counter 1 - ADC Pacer Lower Divider or independent user counter
Source: user connector (Counter 1 In) and optionally,
Counter 2 Out, selectable by software
Gate: Programmable, disabled or user connector (Gate 1)
Output: User connector (Counter 1 Out) and optionally to A/D
start convert, software selectable
Counter 2 - ADC Pacer Upper Divider
Source: Internal 1 MHz oscillator
Gate: Programmable, disabled or user connector (Gate 2)
Output: User connector (Counter 2 Out) and optionally to
counter 1 input, software selectable
Clock input frequency 10 MHz max
High pulse width (clock input) 30 ns min
Low pulse width (clock input) 50 ns min
Gate width high 50 ns min
Gate width low 50 ns min
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage 0.4V max
Output high voltage 3.0V min
Crystal oscillator
Frequency 1 MHz
Frequency accuracy 100 ppm
Digital I/O section
Digital type FPGA
Configuration Two ports, 3 input and 4 output
Input low voltage 0.8V max
Input high voltage 2.0V min
Output low voltage (IOL = 4 mA) 0.32V max
Output high voltage (IOH =
−
4 mA) 3.86V min
Absolute maximum input voltage
−
0.5V , +5.5V
Interrupts Jumper selectable: levels 2, 3, 4, 5, 6, 7 or not connected
Positive-edge triggered
Interrupt enable: Programmable
Interrupt sources: External (IR Input / XCLK), A/D End-of-conversion, A/D FIFO Half-Full
Environmental
Operating temperature range 0 to 50°C
Storage temperature range
−
20 to 70°C
Humidity 0 to 90% non-condensing
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