Jetway Computer NC93 - Manual (Page 26)

21
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable By SPD
* SDRAM CAS Latency Time Auto
* SDRAM Cycle Time Auto
* SDRAM RAS-to-CAS Delay Auto
* SDRAM RAS Precharge Time Auto
System BIOS Cacheable Disabled
Video BIOS Cacheable Disabled
Memory Hole at 15M-16M Disabled
** VGA Setting**
Onchip Frame Buffer Size 8MB
DVMT Mold DVMT
DVMT/FIXED Memory Size 128MB
Menu Level >
↑↓→← Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: Auto, 3, 4 and 5.
SDRAM RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in
the system.
SDRAM Ras Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system.
System BIOS Cacheable