Foxconn 6497MC-RSH User Manual
Page 38
Chapter 3 BIOS Description
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DDR CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS
latency depends on the DRAM timing.
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DRAM Timing Control
Selects whether DRAM timing is controlled by the SPD (Serial Presence Detect)
EEPROM on the DRAM module. Setting to “Auto” enables DRAM timings to be
determined by BIOS based on the configurations on the SPD. Selecting
“Manual” allows users to configure the DRAM timings manually. The setting
values are: Auto, Manual.
Note: The following options can be activated and configured only when this
option is set as “Manual”.
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RAS to CAS Delay (tRCD)
It is used to set the delay time between RAS (Row Address Strobe) and CAS
(Column Address Strobe) signals. The setting values are: 2T, 3T, 4T, 5T.
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Precharge Time (tRP)
It is used to set the precharge time of RAS. The setting values are: 2T, 3T, 4T,
5T.
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RAS to Active Time (tRCD)
It is used to set the RAS to active time. The setting values are: 4T-15T.
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Write Recovery Time (tWR)
It is used to set the write recovery time. The setting values are: 1T, 2T, 3T, 4T,
5T, 6T.
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DDR 128-Bit Access
It is used to set whether 128-bit access is allowed or not.
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ECC Data Check
It is used to enable or disable ECC data check function.
DRAM Clock/
Timing Control Menu
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