Artesyn COMX-P4080-2G-ENP2 Installation and Use (August 2014) - Manual (Page 55)

Chapter 5
COMX-P4080-2G-ENP2 Installation and Use (6806800P63B) 55
Clock Structure
The COMX-P4080-2G-ENP2 needs several kinds of single ended and differential clocks for
booting up and normal operating. Following is the clock distribution tree:
For ruggedized variant where dip switches are not mounted, the following signals connects to
COM Express connector and will be up to carrier to configure them:
Figure 5-1 Clock Distribution
SERDES bank 1 reference
clock select (pin B97 on
COME) SERDES bank 2 reference
clock select (pin B98 on
COME) SERDES bank 2 reference
clock select (pin B98 on
COME)
Bank1_SEL_FS0=0,
100MHz Bank2_SEL_S1=0,
100MHz Bank2_SEL_S1=0,
100MHz
Bank1_SEL_FS0=1,
125MHz Bank2_SEL_S1=1,
125MHz Bank2_SEL_S1=1,
125MHz
*Default:100MHz *Default:125MHz *Default:125MHz