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3 memory, 1 sdram, Figure 4-2 – Artesyn COMX-P2020 Installation and Use (July 2014) User Manual

Page 77: P2020 processor block diagram

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Functional Description

COMX-P2020 COM Express Module Installation and Use (6806800K97D)

77

The integrated L2 Cache/SRAM can be configured as Cache or SRAM. For COMX-P2020, it is
configured as 512 KB L2 cache that is organized as 2048 eight way sets of 32 byte cache lines
based on 36 bit physical addresses.

4.3

Memory

The U-boot will configure the memory controller with the fixed parameter instead of SPD
information on the SOUDIMM.

4.3.1

SDRAM

COMX-P2020 COM Express Module only supports 2 GB DDR3 667 MT/s DDR3+ECC arranged in
two ranks in one slot.

Figure 4-2

P2020 Processor Block Diagram