Aplex Technology ARCHMI-716 User Manual
Page 32
ARCHMI-7XX (SBC-7106A) User Manual
31
Pin#
Signal Name
1
+DC12V
2
+DC12V
3
Ground
4
Ground
5
BKLT_EN_OUT
6
BKLT_CTRL
Note:
Pin6 is backlight control signal, support DC or PWM mode, mode select at BIOS
CMOS menu.
15. CN1:
(1.25mm Pitch 2x20 Connector, DF13A-40DP-1.25V), For 18/24-bit LVDS2 output
connector, Fully supported by Parad PS8625(DP to LVDS), the interface features
dual channel 24-bit output. Low Voltage Differential Signaling, A high speed, low
power data transmission standard used for display connections to LCD panels.
Function
Signal Name
Pin#
Signal Name
Function
LVDS
12V_S0
2
1
12V_S0
LVDS
BKLT_EN_OUT
4
3
BKLT_CTRL
Ground
6
5
Ground
LVDS_VDD5
8
7
LVDS_VDD5
LVDS_VDD3
10
9
LVDS_VDD3
Ground
12
11 Ground
LA_D0_P
14
13 LA_D0_N
LA_D1_P
16
15 LA_D1_N
LA_D2_P
18
17 LA_D2_N
LA_D3_P
20
19 LA_D3_N
LA_CLKP
22
21 LA_CLKN
LB_D0_P
24
23 LB_D0_N
LB_D1_P
26
25 LB_D1_N