Zilog eZ80F92 - Manual (Page 53)

eZ80F92 Development Kit
User Manual
UM013911-0607 Operational Description
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Operational Description
The purpose of the eZ80F92 Flash Module as a feature of the eZ80F92
Development Kit is to provide the application developer with a plug-in
tool to evaluate the memory, IrDA, and other features of the eZ80F92
device.
eZ80F92 Flash Module Memory
The eZ80F92 Flash Module comprises both off-chip SRAM and on-chip
Flash memory, which are described below.
Static RAM
The eZ80F92 Flash Module features 512 KB of fast SRAM. Access speed
is typically 50 ns, allowing zero-wait-state operation at 20 MHz. With the
CPU at 20 MHz, SRAM can be accessed with zero wait states in eZ80
mode. CS1_CTL (chip select CS1) can be set to
08h
(no wait states).
Flash Memory
The eZ80F92 Flash Module features 128 KB of Flash memory. This on-
chip memory can be programmed a single byte at a time, or in bursts of up
to 128 bytes. Write operations can be performed using either memory or I/
O instructions. Erasing bytes in Flash memory returns them to a value of
FFh
. Both the MASS ERASE and PAGE ERASE operations are self-
timed by the Flash controller, leaving the CPU free to execute other oper-
ations in parallel. Upon power-up, the on-chip Flash memory is located in
the address range
000000h–01FFFFh
. Four wait states are programmed
in Flash control register
F8h
.
On-chip Flash memory is prioritized over all external Chip Selects, can be
enabled or disabled (power-on enabled), and can be programmed within
any 128 KB address space in the 16 MB address range.
The eZ80F92 Flash Module features the following memory configura-
tions: