Zilog eZ80F92 - Manual (Page 27)

eZ80F92 Development Kit
User Manual
UM013911-0607 Operational Description
23
PC[7:0] 39,41,43,
45,47,49,
51,53 Port C, Bit [7:0] Bidirectional
ID_[2:0] 6,8,10 eZ80Acclaim! ®
Development
Platform ID
Output
CON_DIS 12 Console Disable Input If a shunt is installed between
pins 12 and 14, the Console
function on the eZ80Acclaim!
®
Development Platform is
disabled.
Reserved 16,18
PD[7:0] 22,24,26,
28,30,32,
34,36 Port D, Bit[7:0] Bidirectional
PB[7:0] 40,42,44,
46,48,50,
52,54 Port B, Bit[7:0] Bidirectional
Table 4. GPIO Connector J6* (Continued)
Signal Pin # Function Direction Notes
Note: *All of the signals are driven directly by the CPU.