Zilog eZ80F92 - Manual (Page 24)

eZ80F92 Development Kit
User Manual
eZ80Acclaim!
®
Development Platform UM013911-0607
20
Almost all of the connectors’ signals are received directly from the CPU.
Three input signals, in particular, offer options to the application devel-
oper by disabling certain functions of the eZ80F92 Flash Module.
37 SDA Bidirectional Yes
38 GND
39 FlashWE Output Low No
40 GND
41 CS3 Input Low Yes
42 DIS_IrDA Output Low No
43 RESET Bidirectional Low Yes
44 WAIT Output Pull-Up 10 K
Ω
; Low Yes
45 V
DD
46 GND
47 HALT_SLP Input Low Yes
48 NMI Output Low Yes
49 V
DD
50 Reserved
Table 3. eZ80Acclaim! ® Development Platform
I/O Connector Identification—JP2* (Continued)
Pin # Symbol Signal Direction Active Level eZ80F92 Signal 2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80F92 Module Schematics on pages 65
through 67 .
2. The Power and Ground nets are connected directly to the eZ80F92 device.