Zilog eZ80F92 - Manual (Page 19)

eZ80F92 Development Kit
User Manual
UM013911-0607 Operational Description
15
31 CS0 Input Low Yes
32 CS1 Input Low Yes
33 CS2 Input Low Yes
34 D0 Bidirectional Yes
35 D1 Bidirectional Yes
36 D2 Bidirectional No
37 D3 Bidirectional Yes
38 D4 Bidirectional Yes
39 D5 Bidirectional Yes
40 GND
41 D7 Bidirectional Yes
42 D6 Bidirectional Yes
43 MREQ Bidirectional Low Yes
44 IORQ Bidirectional Low Yes
45 GND
Table 2. eZ80Acclaim! ® Development Platform
Peripheral Bus Connector Identification—JP1* (Continued)
Pin # Symbol Signal Direction Active Level eZ80F92 Signal 2
Notes:
1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from
this table. The entire interface is represented in the eZ80F92 Module Schematics on pages 65
through 67 .
2. The Power and Ground nets are connected directly to the eZ80F92 device.
3. External capacitive loads on RD, WR, IORQ, MREQ, D0–D7 and A0–A23 should be below 10 pF
to satisfy the timing requirements for the eZ80 ® CPU. All unused inputs should be pulled to
either V
DD
or GND, depending on their inactive levels to reduce power consumption and to
reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in
the eZ80F92’s Peripheral Power-Down Register.