ADLINK cPCI-7300 - Manual (Page 65)

C/C++ Libraries • 57
use an 8237-style DMA controller in the host computer and therefore it is not
blocked in 64K maximal groups. PCI-7300A bus mastering works as follows:
1. To set up bus mastering, first do all normal PCI-7300A initialization
necessary to control the board in status mode. This includes testing for the
presence of the PCI BIOS, determining the base addresses, slot number,
vendor and device ID's, I/O or memory, space allocation, etc. Please make
sure your PCI-7300A is plug in a bus master slot, otherwise this function
will not be workable.
2. Load the PCI controller with the count and 32-bit physical address of the
start of previously allocated destination memory which will accept data.
This count is the number of bytes (not longwords!) transferred during the
bus master operation and can be a large number up to 8 million (2^23)
bytes. Since the PCI-7300A transfers are always longwords, this is 2
million longwords (2^21).
3. After the input sampling is started, the input data is stored in the FIFO of
PCI controller. Each bus mastering data transfer continually tests if any
data in the FIFO and then blocks transfer, the system will continuously
loop until the conditions are satisfied again but will not exit the block
transfer cycle if the block count is not complete. If there is momentarily no
input data, the PCI-7300A will relinquish the bus temporarily but returns
immediately when more input data appear. This operation continues until
the whole block is done.
4. This operation proceeds transparently until the PCI controller transfer byte
count is reached. All normal PCI bus operation applies here such as a
receiver which cannot accept the transfers, higher priority devices
requesting the PCI bus, etc. Remember that only one PCI initiator can
have bus mastering at any one time. However, review the PCI priority and
"fairness" rules. Also study the effects of the Latency Timer. And be aware
that the PCI priority strategy (round robin rotated, fixed priority, custom,
etc.) is unique to your host PC and is explicitly not defined by the PCI
standard. You must determine this priority scheme for your own PC (or
replace it).
5. The interrupt request from the PCI controller can be optionally set up to
indicate that this longword count is complete although this can also be
determined by polling the PCI controller.