ADLINK PCIe-7200 - Manual (Page 42)

Operation Theory 33
4.3 External Clock Mode
The digital input is clocked by external strobe, which is from Pin 19
(I_REQ) of CN2 (PCI/PCIe-7200) or Pin 24 of CN1 (cPCI-7200).
The operation sequence is very similar to the Timer Pacer Trigger.
The only difference is the clock source.
1. The external input strobe is generated from outside
device, and goes through the Pin 19 (I_REQ) of CN2 to
latch the digital input.
2. The digital input data is saved in FIFO after an I/O strobe
signal is coming in.
3. The data saved in input FIFO will be transferred to main
memory on your computer system directly. This is con-
trolled by bus mastering DMA control, this function is
supported by PCI.
To Digital Input Trigger
Latch Digital
Input Data
Digital Input FIFO Bus mastering
DMA data Transfer
PC's Main Memory
1
2
3
Pin 19 of CN2