ADLINK PCI-7224 - Manual (Page 39)

Operation Theorem
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4.3.4 Interrupt Source Control
In ISC register (offset 0x20), there are four bits to control the IRQ sources of
INT1 and INT2.
If the application requires only one IRQ, one of the IRQ sources can be
disabled by software. If no IRQ source is required, both interrupts can be
disabled. However if the user only disables the IRQ source without changing
the initial condition of the PCI controller, the PCI BIOS will still assign a IRQ
level to the PCI card and occupy the PC resource.
It is not recommended to change the initial condition of the PCI card by the
user’s own application software. If the user wishes to disable the IRQ level,
they can use ADLINK’s utility ‘INIT7248.EXE’ or ‘INIT7296.EXE’ to change
power on interrupt setting.
Table 4.3 shows the register format of the ISC (address offset 0x20). This
register is write only. The four LSBs are used to control the source of INT1
and INT2.
INT1 D3 D2 D1 D0 IRQ Source IRQ Trigger Condition
Disable X X 0 0 INT1 disable --
Mode 1 X X 0 1 ~P1C0 falling edge of P1C0
Mode 2 X X 1 0 P1C0 OR ~P1C3 (see following)
Mode 3 X X 1 1 Event Counter Counter count down to 0
INT2 D3 D2 D1 D0 IRQ Source IRQ Trigger Condition
Disable 0 0 X X INT2 disable --
Mode 1 0 1 X X ~P2C0 falling edge of P2C0(*)
Mode 2 1 0 X X P2C0 OR ~P2C3 (see following) (*)
Mode 3 1 1 X X Timer Output Timer count down to 0
Table 4.3 ISC register format
(*) Note: Not available on PCI-7224.
When the IRQ source is set as P1C0 OR P1C3, the IRQ trigger conditions
are summarized in table 4.4.
P1/2C0 P1/2C3 IRQ Trigger Condition
High X PC0=H disable all IRQ
X Low PC3=L disable all IRQ
Low 1->0 PC3 falling edge trigger when PC0=L
0->1 High PC0 rising edge trigger when PC3=H
Table 4.4 IRQ Trigger conditions
Because P1/P2C0 and P1/P2C3 are external signals, the user can utilize the
combination of the four signals to generate a proper IRQ.
4.4 12V and 5V Power Supply