ADLINK PCI-7224 - Manual (Page 33)

Operation Theorem
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4
Operation Theorem
4.1 Digital I/O Ports
4.1.1 Introduction
The 7248/96 products can emulate one/two/four mode 0 configuration of
8255 programmable peripheral interface (PPI) chips. There are 24 DIO
signals for every PPI.
4.1.2 8255 Mode 0
The basic functions of 8255 mode 0 are:
z Two 8-bit I/O ports-port A (PA) and port B (PB)
z Two nibble-wide (4-bit) ports C-PC upper and PC lower
z Each port can be used as either input or output
z Outputs are latched whereas inputs are buffered
z 16 different input/output configurations are available
4.1.3 Special Function of the DIO Signals
Two I/O signals (PC0 and PC3) of CN1 and CN2 can be used to generate
hardware interrupt. Refer to section 4.3 for details on the interrupt control. In
addition, the P1C4 signals can be used as input signal of event counter.