Programming the rs-485 -4, 4 programming the rs-485 – Acrosser AR-B1320 User Manual
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5-4
5.4
PROGRAMMING THE RS-485
The majority of the communicative operations of the RS-485 are the same as the RS-232. When
the RS-485 proceeds with the transmission which needs to control the DTR(TXC) signal, the
installation steps are as follows:
Step 1:
Enable DTR (Data Terminal Relay)
Step 2:
Send out data
Step 3:
Wait for data to empty
Step 4:
Disable DTR
NOTE: Please refer to the section of the “Serial Port” in the chapter “System Controller”
for the detailed description of the COM port’s registers.
(1) Initializing the COM port
Step 1:
Initialize the COM port in the receiver interrupt mode, and /or transmitter interrupt mode. (All
of the communication protocol buses of the RS-485 are the same.)
Step 2:
Disable DTR (Data Terminal Relay) the bit 0 of the address of offset+4 just sets to “0”.
➥
➥
➥
➥NOTE: Control the AR-B1320 CPU card’s DTR signal to enable/disable the RS-485’s TXC
communication.
(2) Send out one character (Transmit)
Step 1:
Enable the DTR signal, and the bit 0 of the address of offset+4 just sets to “1”.
Step 2:
Send out the data. (Write this character to the offset+0 of the current COM port address)
Step 3:
Wait for the buffer’s data to empty. Check the transmitter holding register (THRE, bit 5 of
the address of offset+5), and transmitter shift register (TSRE, bit 6 of the address of
offset+5) so that all sets are set to “0”.
Step 4:
Disable the DTR signal, and the bit 0 of the address of offset+4 sets to “0”
(3) Send out one block data (Transmit – the data can be more than two characters long)
Step 1: Enable the DTR signal, and the bit 0 of the address of offset+4 just sets to “1”.
Step 2: Send out the data. (Write all data to the offset+0 of the current COM port address)
Step 3: Wait for the buffer’s data to empty. Check the transmitter holding register (THRE, bit 5 of
the address of offset+5), and transmitter shift register (TSRE, bit 6 of the address of
offset+5) so that all sets are set to “0”.
Step 4: Disabled DTR signal, and the bit 0 of the address of offset+4 sets to “0”